`timescale 1 ns / 1 ps
module ads8865_tb;

reg clk;
reg rst_n;
wire            co;
reg             co1;
reg             co2;
reg             rd_exec;
wire            dout;
wire             convst;
wire             sclk;
wire [ 15:0 ]    DATA;    
wire             rd_ready;
    initial begin
        clk<=0;
        rst_n<=1;
        #50 rst_n <=0;
        #100 rst_n <=1;
        rd_exec<=1'b0;
    end

        always #5 clk=~clk;
ads8865 u_ads8865(.clk(sclk),.convst(convst),.dout(dout));


always @(posedge clk)begin
    co1<=co;
    co2<=co1;
    if (co1==1&&co2==0) begin
        rd_exec<=1'b1;
    end
    else begin
        rd_exec <= 1'b0;
    end
end

Counter #(2000) sclk_gen_counter (.clk(clk), .rst_n(rst_n), .en( 1'b1), .cnt(),.co(co));
ads8865_driver u_ads8865_driver(
    .clk    (clk    ),
    .rst_n  (rst_n  ),
    .rd_exec(rd_exec),
    .din   (dout   ),
    .convst (convst ),
    .sclk   (sclk   ),
    .rd_data   (DATA   ),
    .rd_ready(rd_ready)
);

endmodule  


module ads8865
(
    input   wire clk,
    input   wire convst,
    output  reg dout
);

always @(posedge clk) begin
    dout<=1;


end 
endmodule  

module Counter #(
    parameter M = 100
)(
    input wire clk, rst_n, en,
    output reg [$clog2(M) - 1 : 0] cnt,
    output wire co
);
    assign co = en & (cnt == M - 1);
    always@(posedge clk) begin
        if(!rst_n) cnt <= 1'b0;
        else if(en) begin
            if(cnt < M - 1) cnt <= cnt + 1'b1;
            else cnt <= 1'b0;
        end
    end
endmodule